Plasma processing of semiconductor wafers in the manufacture of microelectronic integrated circuits is used in dielectric etching, metal etching, chemical vapor deposition and other processes. Such plasma processes require precise control of process parameters, such as the amount of plasma power delivered to the plasma, for example. This parameter is affected by a number of variables, including the ability of the impedance matching device between the plasma source power generator and the reactor's RF power applicator to provide an impedance match over a widely varying plasma load impedance. The wide range of plasma load impedance is attributable to changing conditions within the reactor chamber. As described in U.S. Pat. No. 6,528,751 referenced above, this problem is addressed by a fixed impedance match device, such as a tuning stub or a strip line circuit, that couples source power to the ceiling electrode and has a wide match space. As described in the referenced patent, the reactance of the electrode is selected so that the electrode and plasma resonate at a plasma electrode resonant frequency. Further, the resonant frequency of the fixed match device, the electrode-plasma resonance and the source power frequency are all nearly equal and lie in the VHF range. One advantage is that the fixed match device has a very wide match space, so that the system is less sensitive to variations in plasma load impedance (so that such variations do not greatly affect the amount of source power delivered to the plasma). Even greater imperviousness to variations in plasma load impedance is obtained by providing a slight deviation between these three frequencies, as described in the above-referenced patent.
In this type of reactor, the ceiling electrode is critical, since it couples the source power to the plasma. Variations in the ceiling electrode characteristics or behavior will cause variations in the source power delivered to the plasma. Precise control of the power delivered to the plasma is required now more than ever because of shrinking microelectronic device geometries which reduce the tolerance in etch rate and therefore plasma density and source power. Several problems can cause the ceiling electrode to perturb the RF source power delivered to the plasma, thereby making it impossible to control the delivered source power within the requisite tolerances. One problem is the tendency of the plasma to corrode or etch the interior surface of the ceiling electrode, thereby changing the characteristics of the ceiling electrode. Another problem is the tendency of process gases inside gas delivery passages within the ceiling electrode to arc, thereby absorbing RF power that would otherwise have been delivered to the plasma.
The electrode corrosion problem is addressed by coating the interior surface of the ceiling electrode with a process-compatible layer, specifically a semiconductor layer such as a silicon carbide layer, as will be described below. But this introduces a new problem tending to affect the power delivered to the plasma: the semiconductor layer tends to absorb some of the RF power applied to the ceiling electrode, and the amount absorbed varies greatly with small variations in the characteristics of the semiconductor layer, such as thickness, impurity concentration, temperature, etc. This makes it impossible or extraordinarily expensive to reproduce identical behavior in different reactors of identical design. It also makes it difficult to control the power delivered to the plasma because of unavoidable variations in ceiling temperature. Extremely precise control over impurity concentration and/or thickness of the semiconductor coating may be required to avoid unacceptable variations in RF power absorption, but such tight control over material composition and/or layer thickness is extremely expensive. One aspect of the present invention concerns a way of providing a semiconductor layer or coating on the ceiling electrode without such great variances in electrical behavior of the coating, but without requiring concomitantly tighter control over electrode temperature, impurity concentration or thickness.
The problem of arcing by process gases in the gas injection orifices within the ceiling electrode is caused by a large voltage drop in the axial direction across the ceiling electrode from the large RF source power coupled to the ceiling electrode. It is exacerbated by a large pressure drop across axially extending process gas passages within the ceiling electrode. The combination of a large voltage drop and a large pressure drop in the axial direction across the ceiling electrode almost guarantees the existence of a combination of electric field and pressure levels that permits arcing within gas passages in the ceiling electrode. The large pressure drop within the ceiling electrode gas passages is unavoidable if the gas passages have good gas conductance (as is required). The large electric field is unavoidable due to the large RF source power applied to the electrode. One aspect of the invention concerns a ceiling electrode structure that is impervious to such arcing because it avoids large pressure drops in regions of high electric fields, but without any sacrifice of gas conductance through the process gas orifices or passages in the ceiling electrode.
Recently issued U.S. Pat. No. 6,586,886, also assigned to the present assignee, discloses an all-silicon carbide electrode having a relatively complex structure including two separately machined silicon carbide plates, the front plate having a set of openings and the back plate having a set of pucks that nest in the openings of the front plate to constrict the openings to desired shapes. An approach of the present invention is to avoid such a complex structure, and instead employ a single semiconductor (silicon carbide) layer bonded directly to a metal (aluminum) electrode by an adhesive layer therebetween, with a desired opening shape formed completely in the semiconductor layer, greatly simplifying the electrode structure. One problem with this approach is contamination due to plasma contact with the adhesive layer and outgassing from volatile compounds in the adhesive layer. Such plasma contact with and outgassing from the adhesive layer produce particulate contamination on the wafer being processed. One aspect of the present invention solves the problem of contamination from the adhesive layer.
A related problem is the occurrence of large shear forces across the adhesive layer (between the semiconductor layer and the metal ceiling electrode) attributable to different thermal coefficients of expansion of the semiconductor coating and the metal ceiling electrode. This problem arises particularly in connection with a cleaning process of the present invention that further reduces contamination, requiring the electrode/semiconductor layer temperature to be raised significantly beyond the operating temperature. The temperature excursion from room temperature through the operating temperature to an elevated bakeout temperature creates very high shear forces across the adhesive layer. Such shear forces tend to shatter the electrode/semiconductor coating structure. One aspect of the present invention solves the problem of shattering across the adhesive layer due to the large temperature excursions of the ceiling electrode cleaning process.